1. Field of the Invention
The invention in general relates to the fabrication of layered superlattice materials, and more particularly to fabrication processes that provide high-polarizability and low fatigue ferroelectric integrated circuit devices and low-leakage current high dielectric constant integrated circuit devices using low processing temperatures.
2. Statement of the Problem
Ferroelectric compounds possess favorable characteristics for use in nonvolatile integrated circuit memories. See Miller, U.S. Pat. No. 5,046,043. A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, and low leakage current. Layered superlattice material oxides have been studied for use in integrated circuits. U.S. Pat. No. 5,434,102, issued Jul. 18, 1995, to Watanabe et. al., and U.S. Pat. No. 5,468,684, issued Nov. 21, 1995, to Yoshimori et al., describe processes for integrating these materials into practical integrated circuits. Layered superlattice materials exhibit characteristics in ferroelectric memories that are orders of magnitude superior to alternative types of ferroelectric materials, such as PZT and PLZT compounds.
Integrated circuit devices containing ferroelectric elements with layered superlattice materials are currently being manufactured. The layered superlattice materials comprise metal oxides. The presence of oxides causes problems because the oxygen diffuses through the various materials contained in the integrated circuit and combines with atoms in the substrate and in semiconductor layers forming oxides. The resulting oxides interfere with the function of the integrated circuit; for example, they may act as dielectrics in the semiconducting regions, there by virtually forming capacitors. Diffusion of atoms from the underlying substrate and other circuit layers into the ferroelectric metal oxide is also a problem; for example, silicon from a silicon substrate and from polycrystalline silicon contact layers is known to diffuse into layered superlattice material and degrade its ferroelectric properties. For relatively low-density applications, the ferroelectric memory capacitor is placed on the side of the underlying CMOS circuit, and this may reduce somewhat the problem of undesirable diffusion of atoms between circuit elements. Nevertheless, as the market demand and the technological ability to manufacture high-density circuits increase, the distance between circuit elements decreases, and the problem of molecular and atomic diffusion between elements becomes more acute. To achieve high circuit density by reducing circuit area, the ferroelectric capacitor of a memory cell is placed virtually on top of the switch element, typically a field-effect transistor (hereinafter "FET"), and the switch and bottom electrode of the capacitor are electrically connected by a conductive plug. To inhibit undesired diffusion, a barrier layer is located under the ferroelectric oxide, between the capacitor's bottom electrode and the underlying layers. The barrier layer not only must inhibit the diffusion of oxygen and other chemical species that may cause problems; it must also be electrically conductive, to enable electrical connection between the capacitor and the switch. The maximum processing temperature allowable with current barrier technology is about 700.degree. C. At temperatures above 700.degree. C., the highest-temperature barrier materials degrade and lose their diffusion-barrier properties. On the other hand, the minimum feasible manufacturing process temperatures of layered superlattice materials used in the prior art is about 800.degree. C., which is the temperature at which deposited layered superlattice materials are annealed to achieve good crystallization. Good ferroelectric properties have been achieved in the prior art using process heating temperatures at about 700.degree. C. See U.S. Pat. No. 5,508,226, issued Apr. 16, 1996, to Ito et. al. Nevertheless, the annealing and other heating times in the low-temperature methods disclosed in the prior art are in the range of three to six hours, which is economically unfeasible.
For the above reasons, therefore, it would be useful to have a low-temperature method for fabricating layered superlattice materials in ferroelectric integrated circuits in which the heating time was much less than three to six hours.